1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, in particular, the present invention pertains to methods and circuits in a semiconductor memory device to obtain reduced circuit area, improved speed and simplified operation in connection with relocating data within the memory device.
2. Description of the Prior Art
With the recent appearance of video random access memory (VRAM), many systems makers have used a graphic buffer such as the VRAM to improve the performance of the system. More recently, a window RAM (WRAM), has become available to provide even greater improvements in performance with respect to graphic display applications. The basic function of the WRAM is to relocate data, for example by moving data, "from a DRAM to a latch, and from a latch to a DRAM". Operations of this type support screen display functions such as a block move, scrolling, etc. a high speed.
FIG. 1 is a simplified circuit diagram of a conventional semiconductor memory device having an internal data read/write function. The memory device of FIG. 1 is provided with a memory cell array 10 composed of a plurality of memory cells coupled to a plurality of bit lines, respectively, a plurality of column selection sections 20, coupled between the plurality of bit lines and an input/output data line L, for transmitting data read out from a source location in the memory array onto the input/output data line L in response to a corresponding source column selection signal. The read data applied to the input/output data line L is then transmitted to a destination location in response to a destination column selection signal CSL2 which is generated subsequently to the source column selection signal CSL1. To support these operations, a data amplifying section 40 comprising a sense amp is coupled to the input/output data line L for amplifying the read-out source data, and a latch section 60 is connected to the sense amp for latching the resulting output data. A write drive section 80 drives the latched data from the latch section 60 to the input/output data line L. This circuitry is repeated for each I/O line although only one line is shown for illustration. Further details are omitted as they are well known in the semiconductor memory art.
The operation of the conventional memory device as constructed above will be explained. A bit line of the memory cell array 10 is designated by a corresponding source address for reading out a pixel data (hereinafter referred to as "data"), and a switching transistor in the column selection section 20 is turned on when the corresponding source column selection signal CSL1 is asserted to the column selection section 20. Accordingly, the internal data of the memory cell array is carried on the input/output bus composed of a plurality of bits through the corresponding switching transistors. The data on the input/output bus is amplified by a predetermined amplification factor by the data amplifying section 40, i.e., a sense amplifier, and then latched in the latch section 60.
FIG. 2 illustrates the movement or relocation of a text character on a display screen. Referring to FIG. 2, in order to move the data being displayed on the screen to another position of the screen, an address movement of the data is required in a frame buffer such as VRAM, WRAM, DRAM, etc. In other words, the data are relocated in the frame buffer memory. This can be done internally.
According to prior art, relocation of the data is performed through a latch cell which provides a data moving path such as "from a DRAM to a latch", and "from a latch to a DRAM" in the frame buffer so that the data is read out from the memory and then the read-out data is written in another address of the memory.
When a destination column selection signal CSL2 is provided to the column selection section 20 to store the data in a desired destination address of the memory, a corresponding selection transistor is turned on, and thus the data maintained in the latch section 60 is transferred on the input/output data line L through the write drive section 60, i.e., a write driver WRDRV, causing the data to be stored in the corresponding address of the memory cell array 10 through the switching transistor.
FIG. 3 is a timing diagram further illustrating operation of the conventional memory device. Referring to FIG. 3, the data is read out from the memory cell array 10 during a cycle when the source column selection signal CSL1 and a read drive signal UFBR are activated and a column address strobe signal CASB is activated with a `low` level. The read-out data is maintained in the latch section 60 via the switching transistor, the input/output data line, and the sense amplifier. Thereafter, the state of "Don't care" is maintained for a predetermined period, and then the data maintained in the latch section 60 is stored in the memory cell array via the write drive section 80, the input/output data line L, and the switching transistor during another cycle when the destination source column selection signal CSL2 and a write drive signal UFBWL are activated and the column address strobe signal CASB is activated with a `low` level. As a result, the data movement in the memory is performed during two cycles.
One can estimate the speed of data transmission achieved by the above-described data transmission method using two cycles, as follows. Assume, for example, data output is composed of 32 bits, the number of the open state of the simultaneous selection signal CSL is 8 in each of four memory core blocks, and the cycle time is 20 ns. In this illustration, since the data movement through the internal bus in a cycle is 1.6 GBytes/Second (8*32 Bits/20 ns) maximum, and the data moving time in the core cell of 8*32 Bits requires 40 ns (two cycles), the data movement for one second will be 0.8 Giga Bytes.
As described above, the data is carried on the input/output data line in response to the source and destination selection signals CSL1 and CSL2. The numbers of the input/output data lines L, the sense amplifiers S/A of the data amplifying section 40, the input/output drivers IODRV, and the latches of the write drive section 80 equally increase corresponding to the number of selection signals to be gated. In other words, all of these elements are duplicated for each bit in a memory word or row. Consequently, while bandwidth can be increased by increasing word size, the chip size and manufacturing costs while increase as well. Accordingly, the need remains to improve speed of operation in a frame buffer memory or the like without increasing chip area or word size.